Deep trench capacitor with scallop profile

ABSTRACT

The present disclosure relates to an integrated chip having a deep trench capacitor with serrated sidewalls defining curved depressions, and a method of formation. In some embodiments, the integrated chip includes a substrate having a trench with serrated sidewalls defining a plurality of curved depressions. A layer of dielectric material conformally lines the serrated sidewalls, and a layer of conductive material is arranged within the trench and is separated from the substrate by the layer of dielectric material. The layer of dielectric material is configured as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate. The serrated sidewalls of the layer of conductive material increase a surface area of exterior surfaces of the layer of conductive material, thereby increasing a capacitance of the capacitor per unit of depth

REFERENCE TO RELATED APPLICATION

This Application claims priority to U.S. Provisional Application No. 62/272,220 filed on Dec. 29, 2015, the contents of which is hereby incorporated by reference in its entirety.

BACKGROUND

The semiconductor industry has continually tried to decrease the surface area of semiconductor devices to fit more devices on a same substrate size. Vertical device structures can greatly reduce the surface area requirement for a semiconductor device. One type of vertical device that is commonly implemented in integrated chips is deep trench capacitors. Deep trench capacitors comprise one or more capacitor electrodes that extend into a trench within a semiconductor substrate. They can be used for a myriad of purposes, such as decoupling capacitors that are configured to decouple one part of an electrical circuit, such as interconnect, from another part of the circuit, for example.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIG. 1 illustrates a cross-sectional view of some embodiments of an integrated chip having a deep trench capacitor within a trench comprising serrated sidewalls defining a plurality of curved depressions.

FIG. 2 illustrates a cross-sectional view of some additional embodiments of an integrated chip having a deep trench capacitor within a trench having serrated sidewalls.

FIG. 3 illustrates a cross-sectional view of some additional embodiments of an integrated chip having a deep trench capacitor within a trench having serrated sidewalls.

FIGS. 4A-4C illustrate cross-sectional views of some additional embodiments of an integrated chip having a deep trench capacitor within a trench having serrated interior surfaces.

FIGS. 5-7 illustrate a cross-sectional view of some additional embodiments of an integrated chip having a deep trench capacitor within a trench having serrated interior surfaces.

FIGS. 8-13 illustrate cross-sectional views of some additional embodiments of a method of forming a deep trench capacitor within a trench having serrated sidewalls.

FIG. 14 illustrates a flow diagram of some embodiments of a method of forming a deep trench capacitor within a trench having serrated sidewalls.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

Deep trench capacitors are capacitors that are formed within trenches extending into a semiconductor substrate. Typically, deep trench capacitors are formed by etching the substrate to form a trench, into which a conductive material and a dielectric material are subsequently formed. As the size of integrated chip components decreases, the depth of the deep trenches can cause a number of issues. For example, in multi-tiered three-dimensional integrated chip (3DIC) substrates are often thinned prior to bonding. However, deep trenches may inhibit substrate thinning, thereby increasing the length of inter-tier interconnections between stacked substrates. Furthermore, while the vertical sidewalls of deep trench capacitors allow for the capacitors to scale well, as the distance between the capacitors decreases it results in a weak structural integrity of the substrate along the edge due to decreasing silicon density. The decreased structural integrity can lead to integrated chip failure, which is costly to integrated chip manufacturers.

The present disclosure relates to an integrated chip having a deep trench capacitor arranged within a trench having serrated sidewalls defining a plurality of curved depressions, and a method of formation. The curved depressions increase a surface area of capacitive electrodes of a deep trench capacitor within the trench, thereby allowing for the capacitor to have a greater capacitance per unit depth. In some embodiments, the integrated chip comprises a substrate having a trench with serrated sidewalls defining a plurality of curved depressions. A layer of dielectric material conformally lines the serrated sidewalls, and a layer of conductive material is arranged within the trench and is separated from the substrate by the layer of dielectric material. The layer of dielectric material is configured as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.

FIG. 1 illustrates a cross-sectional view of some embodiments of an integrated chip 100 having a deep trench capacitor 101 arranged within a trench comprising serrated sidewalls defining a plurality of curved depressions.

The integrated chip 100 comprises a substrate 102 having a conductive doped region 104. In some embodiments, the substrate 102 comprises a semiconductor material (e.g., silicon) having a first doping type (e.g., n-type). The conductive doped region 104 may have a second doping type (e.g., p-type) that is different than the first doping type. Capacitor components are disposed in a trench 106 that extends from an upper surface 102 u of the substrate 102 to an underlying location within the conductive doped region 104. The trench 106 has serrated sidewalls that respectively define a plurality of curved depressions 108.

Capacitor components may include a layer of dielectric material 110 is arranged within the trench 106. In some embodiments, the layer of dielectric material 110 may conformally line the serrated sidewalls of the trench 106. Conductive material 112 is also arranged within the trench 106. The conductive material 112 has sidewalls comprising a plurality of curved protrusions 114 facing the serrated sidewalls of the trench 106. In some embodiments, the conductive material 112 is vertically and laterally separated from the substrate 102 by the layer of dielectric material 110.

In some embodiments, the conductive doped region 104 is configured to act as a first capacitor electrode (E₁) of a deep trench capacitor 101. The conductive material 112 is configured to act as a second capacitor electrode (E₂), which is separated from the first electrode (E₁) by the layer of dielectric material 110 to give the deep trench capacitor 101 a capacitance C. Since the capacitance C is based upon charges on the first capacitor electrode (E₁) and the second capacitor electrode (E₂), the capacitance C is proportional a surface area of interior surfaces of the trench 106 and a surface area of exterior surfaces of the conductive material 112. The serrated sidewalls of the trench 106 and the conductive material 112 increase a surface area of the interior surfaces of the trench 106 and the exterior surfaces of the conductive material 112, thereby increasing a capacitance of the deep trench capacitor 101 per unit of depth. In other words, the serrated sidewalls allow for the deep trench capacitor 101 to have a same capacitance as a capacitor having smooth sidewalls at a lesser depth. By reducing the depth of the trench 106, the deep trench capacitor 101 can be formed in a shorter time and can be easily integrated into multi-tiered 3DIC structures.

FIG. 2 illustrates a cross-sectional view of some additional embodiments of an integrated chip 200 having a trench comprising serrated sidewalls.

The integrated chip 200 comprises a trench 106 that extends from an upper surface 102 u of a substrate 102 to an underlying position within the substrate 102. The trench 106 comprises serrated sidewalls defining a plurality of curved depressions 108. In some embodiments, the plurality of curved depressions 108 may comprise arced depressions having substantially arced cross-sections within the sidewall of the trench 106. The arced depressions have a surface area that is proportional to lengths of the arced depressions, so that an arced depression that has an interior surface with an arc length spanning an angle of Φ will have a length 204 that is equal to Φ/360°*h*3.14. For example, a semi-circular arced depression with a height h and an arc length spanning 180° (i.e., a half circle) will have a length 204 (extending along a side of the trench 106 between points A and B) that is equal to 180°/360°*h*3.14=1.57*h.

The curved depressions 108 within the serrated sidewalls increase a sidewall length along a cross-section of the substrate 102 relative to straight sidewalls. For example, for arced depressions comprising semicircular arced depressions a sidewall of the trench 106 will have a length 206 (between points C and D) that is equal to 1.57 times a depth 208 of the trench 106 (e.g., allowing for a disclosed deep trench capacitor having a trench 106 with a depth 208 of approximately 19 um to provide for a same capacitance as a deep trench capacitor with straight trench sidewalls having a depth of approximately 30 um). The increased length 206 increases a capacitance of a deep trench capacitor formed within the trench 106, since the capacitance is defined as: C=ε_(r)ε₀·A/d, where A is an area of overlap of capacitor electrodes, ε_(r) is the relative static permittivity of a dielectric material between the capacitor electrodes, ε₀ is the permittivity of free space (ε₀≈8.854×10⁻¹² F m⁻¹), and d is the distance separating the capacitor electrodes. Thus, the serrated sidewalls allow for a disclosed deep trench capacitor formed within the trench 106 to have a capacitance equal to a capacitor within a trench having straight sidewalls at a smaller trench depth.

FIG. 3 illustrates a cross-sectional view of some additional embodiments of an integrated chip 300 having a deep trench capacitor within a trench comprising serrated sidewalls.

The integrated chip 300 comprises a plurality of trenches 302 respectively extending from an upper surface 102 u of a substrate 102 to an underlying location within the substrate 102. In some embodiments, the plurality of trenches 302 may be arranged within a conductive doped region 104. In such embodiments, a layer of dielectric material 304 is arranged within the plurality of trenches 302, and a layer of conductive material 306 is arranged within the plurality of trenches 302 at locations separated from the substrate 102 by the layer of dielectric material 304.

The one or more trenches 302 comprise sidewalls 302 s defining a plurality of curved depressions. In some embodiments, the one or more trenches 302 also have a bottom surface 308 comprising a curved profile. The one or more trenches 302 respectively define an opening 303 that is arranged along the upper surface 102 u of the substrate 102 and an underlying cavity in communication with the opening 303. The cavity has a width, extending between opposing sidewalls 302 s, which generally increases (e.g., from w₂ to w₂′) as a distance from the upper surface 102 u of the substrate 102 decreases. In some embodiments, the one or more trenches 302 curve inward along top portion thereof (e.g., toward the opening 303), so that the opening 303 has a first width w₁, while the underlying cavity has second width, w₂ or w₂′, that is larger than the first width w₁. The curvature of a trench causes the trench to protrude laterally outward from the opening 303, so that the substrate 102 overhangs the trench along opposing sides.

In some embodiments, the first width w₁ of the opening 303 is smaller than the smallest width of the underlying cavity (i.e., w₁<w₂<w₂′). In some embodiments, the width w₂′ may be in a range of between approximately ⅙^(th) and approximately to 1/7^(th) a depth d of the one or more trenches 302 (e.g., for a trench with a depth d of 19 um, w₂′ may be in a range of between approximately 2.5 um and approximately 3.5 um). In some embodiments, the width w₂ may be in a range of between approximately ⅛^(th) and approximately to 1/9^(th) the depth d of the one or more trenches 302 (e.g., for a trench with a depth d of 19 um, w₂ may be in a range of between approximately 2.0 and approximately 3.0 um). In some embodiments, the width w₁ may be in a range of between approximately 1/11^(th) and approximately to 1/12^(th) the depth d of the one or more trenches 302 (e.g., for a trench with a depth d of 19 um, w₁ may be in a range of between approximately 1.5 um and approximately 2.5 um).

In some embodiments, the sidewalls 302 s of the one or more trenches 302 are angled with respect to a normal line 310 that is perpendicular to the upper surface 102 u of the substrate 102. In some embodiments, sidewall angles of the sidewalls 302 s change along a depth d of a trench. In some embodiments, the sidewall angles (with respect to normal line 310) of the sidewalls 302 s decrease as depths of the one or more trenches 302 increase. For example, in some embodiments, upper sections of the sidewalls 302 s are angled at a first angle Θ₁ with respect to the normal line 310 and lower sections of the sidewalls 302 s are angled at a second angle Θ₂ with respect to the normal line 310, wherein the second angle Θ₂ is smaller than the first angle Θ₁.

Although integrated chip 300 is illustrated as having a capacitor with an electrode comprising the conductive doped region 104, it will be appreciated that in alternative embodiments the conductive doped region 104 may be omitted. For example, in some alternative embodiments, the plurality of trenches 302 may not be arranged within a conductive doped region. In such embodiments, two or more layers of conductive material may be arranged within respectively ones of the plurality of trenches 302. The two or more layers of conductive material are separated by one or more layers of dielectric material and are configured to act as capacitor electrodes.

FIGS. 4A-4C illustrate cross-sectional views of some additional embodiments of an integrated chip 400 having a deep trench capacitor within a trench comprising serrated interior surfaces.

The integrated chip 400 comprises a plurality of trenches 402 extending into a substrate 102. The plurality of trenches 402 comprise serrated interior surfaces defining a plurality of curved depressions. In some embodiments, the serrated interior surfaces may comprise serrated sidewalls. In some embodiment, the serrated interior surfaces may also comprise a bottom surface 408 having a curved profile extending between opposing sidewalls of a trench, which defines a plurality of curved depressions (e.g., arced depressions). The curved depressions along the bottom surface 408 of the plurality of trenches 402 further increase a surface area of interior surfaces of a trench and a surface area of exterior surfaces of a conductive material 306 within the trench.

In some embodiments, the plurality of curved depressions may have a non-uniform depth along a depth of a trench. For example, in some embodiments, the depths of the plurality of curved depressions into the substrate 102 may decrease as a distance from an upper surface 102 u of the substrate 102 increases. For example, in a first section 404, which is shown in FIG. 4A and also in cross-sectional view 410 of FIG. 4B, the curved depressions may have a first depth of d₁. In a second section 406 that is below the first section 404 (i.e., that is further from the upper surface 102 u than the first section 404), the curved depressions may have a second depth of d₂, as shown in FIG. 4A and in cross-sectional view 412 of FIG. 4C. The second depth d₂ is less than the first depth d₁. For example, in some embodiments, the first depth d₁ may be in a range of between approximately 100 nm and approximately 500 nm, while the second depth d₂ may be in a range of between approximately 0 nm and approximately 200 nm.

In some embodiments, as the depths of the curved depressions into the substrate 102 decrease, a slope of the serrated sidewalls of the plurality of trenches 402 increase (i.e., as a depth of the depressions decreases, the sidewall angle of the serrated sidewalls with respect to a normal line perpendicular to the upper surface 102 u decreases).

FIG. 5 illustrates a cross-sectional view of some additional embodiments of an integrated chip 500 having one or more deep trench capacitors within a trench comprising serrated interior surfaces.

The integrated chip 500 comprises a plurality of trenches 502 arranged within a substrate 102 and having serrated sidewalls defining a plurality of curved depressions. A first layer of dielectric material 504 a is conformally arranged along the serrated sidewalls of the plurality of trenches 502. A first layer of conductive material 506 a is conformally arranged along interior sidewalls of the first layer of dielectric material 504 a, so that the first layer of dielectric material 504 a separates the first layer of conductive material 506 a from the substrate 102. A second layer of dielectric material 504 b is conformally arranged along interior surfaces of the first layer of conductive material 506 a. A second layer of conductive material 506 b is conformally arranged along interior sidewalls of the second layer of dielectric material 504 b, so that the second layer of dielectric material 504 b separates the first layer of conductive material 506 a from the second layer of conductive material 506 b.

In some embodiments, the integrated chip 500 comprises a first deep trench capacitor 501 a and a second deep trench capacitor 501 b. The deep trench capacitors, 501 a and 501 b, respectively have a first electrode E₁ comprising the first layer of conductive material 506 a, a second electrode E₂ comprising the second layer of conductive material 506 b, and an intervening capacitor dielectric comprising the second layer of dielectric material 504 b. In some embodiments, the first layer of dielectric material 504 a may be omitted.

FIG. 6 illustrates a cross-sectional view of some additional embodiments of an integrated chip 600 having deep trench capacitors within trenches comprising serrated interior surfaces.

The integrated chip 600 comprises a plurality of trenches 502 having serrated sidewalls defining a plurality of curved depressions which extend into a conductive doped region 104. A first layer of dielectric material 602 a is conformally arranged along the serrated sidewalls of the plurality of trenches 502, and extends outward from the plurality of trenches 502 to locations overlying the substrate 102. A first layer of conductive material 604 a is conformally arranged along interior sidewalls of the first layer of dielectric material 602 a, so that the first layer of dielectric material 602 a separates the first layer of conductive material 604 a from the substrate 102. The first layer of conductive material 604 a also extends outward from the plurality of trenches 502 to locations overlying the substrate 102 and the first layer of dielectric material 602 a.

In some embodiments, a second layer of dielectric material 602 b is conformally arranged along interior sidewalls of the first layer of conductive material 604 a, and extends outward from the plurality of trenches 502 to locations overlying the substrate 102. A second layer of conductive material 604 b is conformally arranged along interior sidewalls of the second layer of dielectric material 602 b, so that the second layer of dielectric material 602 b separates the second layer of conductive material 604 b from the first layer of conductive material 604 a. The second layer of conductive material 604 b also extends outward from the plurality of trenches 502 to locations overlying the substrate 102.

A back-end-of-the-line (BEOL) metallization stack is arranged over the substrate 102. The BEOL metallization stack comprises a plurality of metal interconnect layers arranged within a dielectric structure 606 having one or more inter-level dielectric (ILD) layer 606 a-606 b. In various embodiments, the one or more ILD layers 606 a-606 b may comprise an oxide, an ultra-low k dielectric material, and/or a low-k dielectric material (e.g., SiCO). In some embodiments, the plurality of metal interconnect layers may comprise a first conductive contact 608 a and a second conductive contact 608 b arranged within a first ILD layer 606 a. The first conductive contact 608 a is electrically coupled to the conductive doped region 104 and the second conductive contact 608 b is electrically coupled to the second layer of conductive material 604 b, thereby forming two deep trench capacitors arranged in a series connection. The plurality of metal interconnect layers further comprise metal interconnect wires 610 arranged within a second ILD layer 606 b and electrically coupled to one or more of the conductive contacts 608 a-608 c. In other embodiments, additional contacts may be arranged within the first ILD layer 606 a to form alternative connection types (e.g., parallel connections, decoupled capacitors, etc.).

FIG. 7 illustrates a cross-sectional view of some additional embodiments of an integrated chip 700 having deep trench capacitors within trenches comprising serrated interior surfaces.

The integrated chip 700 comprises a plurality of trenches 402 within a substrate 102, which have serrated sidewalls defining a plurality of curved depressions. A layer of dielectric material 702 is conformally arranged along the serrated sidewalls. The layer of dielectric material 702 extends outward from the plurality of trenches 402 to location overlying the substrate 102. A layer of conductive material 704 is conformally arranged along interior sidewalls of the layer of dielectric material 702, so that the layer of dielectric material 702 separates the layer of conductive material 704 from the substrate 102. The layer of conductive material 704 also extends outward from the plurality of trenches 402 to locations overlying the substrate 102 and the layer of dielectric material 702.

A plurality of metal interconnect layers are arranged within a dielectric structure 706 over the substrate 102. The plurality of metal interconnect layers comprise conductive contacts 708 a-708 c arranged within a first ILD layer 706 a and metal interconnect wires 710 arranged within a second ILD layer 706 b over the first ILD layer 706 a. In some embodiments, the layer of conductive material 704 over the substrate 102 is laterally separated by the dielectric structure 706 to form a first segment of conductive material 704 a and a second segment of conductive material 704 b. In some such embodiments, a first conductive contact 708 a is electrically coupled to conductive doped region 104, a second conductive contact 708 b is electrically coupled to the first segment of conductive material 704 a, and a third conductive contact 708 c is electrically coupled to the second segment of conductive material 704 b, thereby forming two deep trench capacitors arranged in a parallel connection. In other embodiments, additional contacts may be arranged within the first ILD layer 706 a to form alternative connection types (e.g., series connections, decoupled capacitors, etc.).

FIGS. 8-13 illustrate cross-sectionals views of some embodiments of a method of forming a deep trench capacitor within a trench comprising serrated sidewalls. It will be appreciated that elements in FIGS. 8-13 that have been described in previous embodiments have been designated with the same reference numbers for ease of understanding. While the cross-sectional-views shown in FIGS. 8-13 are described with reference to a method of forming a deep trench capacitor, it will be appreciated that the structures shown in the figures are not limited to the method of formation but rather may stand alone separate of the method.

As shown in cross-sectional view 800 of FIG. 8, a conductive doped region 808 may be formed within a substrate 802. In various embodiments, the substrate 802 may be any type of semiconductor body (e.g., silicon, SiGe, SOI) such as a semiconductor wafer and/or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers associated therewith. In some embodiments, the conductive doped region 808 may be formed by an implantation process that selectively implants the substrate 802 with a dopant species 804 (e.g., boron, phosphorous, arsenic, etc.). In some embodiments, the substrate 802 may be selectively implanted according to a first masking layer 806 (e.g., a photoresist layer, a hard mask layer, etc.). In some embodiments, after the implantation process is completed, the dopant species 804 may be driven into the substrate 802 by a high temperature thermal anneal.

As shown in cross-sectional view 900 of FIG. 9, a second masking layer 902 is formed over the substrate 802. The second masking layer 902 may have one or more openings 904 corresponding to trenches that are to be subsequently formed in the substrate 802. In some embodiments, the one or more openings 904 may overlie the conductive doped region 808. In other embodiments, the one or more openings 904 may not overlie a conductive doped region. In some embodiments, the second masking layer 902 may comprise a hardmask layer. In some embodiments, the hardmask layer may comprise a nitride, an oxide, titanium, aluminum, tantalum, zirconium, hafnium, or some combination thereof, for example.

As shown in cross-sectional view 1000 of FIG. 10, one or more trenches 302 are formed within an upper surface 102 u of the substrate 102. The one or more trenches 302 may be formed by selectively etching the substrate 102 with a multi-step etching process. The one or more trenches 302 each define an opening arranged along an upper surface 102 u of the substrate 102 and an underlying cavity. The cavity has a width that extends between opposing sidewalls, and which generally increases (e.g., w₂ to w₂′) from as a distance from the upper surface 102 u of the substrate 102 decreases. In some embodiments, the one or more trenches 302 curve inward along tops of the one or more trenches 302, so that the opening has a first width w₁, while the underlying cavity has a second width, w₂ or w₂′, that is larger than the first width w₁.

The second masking layer 902 comprises serrated sidewall 902 s defining a plurality of curved depressions. Openings within the second masking layer 902 have widths extending between opposing serrated sidewall 902 s. The widths of the openings generally increase as a distance from an upper surface 902 u of the second masking layer 902 decreases. For example, while the width of the openings in the second masking layer 902 may vary due to the plurality of curved depressions, the width generally increases from a width w₁ to a width w₁′ at an overlying position. In some embodiments, the width of the one or more trenches 302 is greater than the width of the openings within the second masking layer 902 along an interface between the substrate 102 and the second masking layer 902.

In some embodiments, the serrated sidewalls 902 s may be oriented at a non-zero angle Θ_(h) with respect to a normal line 310 perpendicular to the upper surface 102 u of the substrate 102. The one or more trenches 302 comprise serrated sidewalls that are oriented at a non-zero angle Θ₁ with respect to the normal line 310. In some embodiments, the non-zero angle Θ_(h) is larger than the second non-zero angle Θ₁. In some embodiments, the slope of the opposing sidewalls of the one or more trenches 302 may increase (decreasing angle Θ₁ with respect to normal line 310) as a distance from the upper surface 102 u of the substrate increases.

In some embodiments, the multi-step etching process used to form the plurality of trenches 302 may comprise a multi-step dry etch process. The multi-step dry etch process comprises a plurality of cycles that respectively perform steps of exposing the substrate to an etchant to form a curved depression within the substrate and then subsequently forming a protective layer on the substrate. Each of the plurality of cycles forms a curved depression within a sidewall of the substrate 102. For example, a first cycle forms a first curved depression within a sidewall, a second cycle forms a second curved depression within the sidewall underlying the first curved depression, etc. In some embodiments, the etchant may comprise a dry etchant using an etching chemistry comprising tetrafluoromethane (CF₄), sulfur hexafluoride (SF₆), and/or nitrogen trifluoride (NF₃), for example. In some embodiments, the protective layer may be formed by exposing the substrate to a polymer gas (e.g., C₄F₈). In some embodiments, within a cycle a first gas may be introduced into a processing chamber to perform an etch during a first time period, the processing chamber may be purged, and then a second gas species may be in-situ (i.e., without breaking a vacuum) introduced into the process chamber to form a protective layer during a subsequent time period.

In some embodiments, the second masking layer 902 may be removed after the multi-step etching process is completed. In other embodiments (not shown), the second masking layer 902 may be left in place after the multi-step etching process is completed. In such embodiments, additional layers (e.g., layers of conductive material, layers of dielectric material, ILD layers, etc.) may be subsequently formed over the second masking layer 902.

As shown in cross-sectional view 1100 of FIG. 11, a layer of dielectric material 1102 is conformally formed along the serrated sidewalls of the one or more trenches 302. Because the layer of dielectric material 1102 is conformally formed along the serrated sidewalls, the layer of dielectric material 1102 also has serrated sidewalls. In various embodiments, the layer of dielectric material 304 may comprise an oxide or a nitride, for example. In some embodiments, the layer of dielectric material 1102 may be formed using a deposition process such as a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PE-CVD) process, an atomic layer deposition (ALD) process, etc. In other embodiments, the layer of dielectric material 1102 may be formed using a thermal process.

In some embodiments, the layer of dielectric material 1102 may also be formed along an upper surface 102 u of the substrate 102. In some such embodiments, an etching process may be used to pattern the layer of dielectric material 1102 over the substrate 102. The etching process may comprise forming a masking layer (e.g., a patterned photoresist layer formed using a photolithography process) and then etching the layer of dielectric material 1102 using the masking layer. In some additional embodiments, a planarization process may be performed on the layer of dielectric material 1102 after the deposition is completed. In some embodiments, the planarization process may comprise a chemical mechanical polishing (CMP) process.

As shown in cross-sectional view 1200 of FIG. 12, a layer of conductive material 1202 is conformally formed along the serrated sidewalls of the layer of dielectric material 1102. Because the layer of conductive material 1202 is conformally formed along the serrated sidewalls of the layer of dielectric material 1102, the layer of conductive material 1202 also has serrated sidewalls. In various embodiments, the layer of conductive material 1202 may comprise a metal such as copper, aluminum, tungsten, etc. In other embodiments, the layer of conductive material 1202 may comprise doped polysilicon. In some embodiments, the layer of conductive material 1202 may be formed using a deposition process (e.g., PE-CVD, CVD, PVD, ALD, etc.) and/or a plating process (e.g., electroplating, electro-less plating, etc.).

In some embodiments, the layer of conductive material 1202 may also be formed over upper surfaces of the substrate 102 and the layer of dielectric material 1102. In some such embodiments, an etching process may be used to pattern the layer of conductive material 1202. In some additional embodiments, a planarization process (e.g., a CMP process) may be performed on the layer of conductive material 1202 after the deposition is completed.

As shown in cross-sectional view 1300 of FIG. 13, a plurality of conductive contacts 1304 a-1304 b are formed within a dielectric structure 1302 overlying the substrate 102. In some embodiments, the plurality of conductive contacts 1304 a-1304 b may be formed by depositing a first inter-level dielectric (ILD) layer 1302 a over the substrate 102. The first ILD layer 1302 a is selectively etched to form contact holes. The contact holes are then filled with a conductive material (e.g., tungsten) to form the plurality of conductive contacts 1304 a-1304 b. A plurality of metal interconnect wires 1306 may be subsequently formed in a second ILD layer 1302 b overlying the first ILD layer 1302 a. In some embodiments, the first ILD layer 1302 a may be deposited by a physical vapor deposition technique (e.g., PVD, CVD, PE-CVD, ALD, etc.). T In some embodiments, the plurality of conductive contacts 1304 a-1304 b may be formed using a deposition process and/or a plating process (e.g., electroplating, electro-less plating, etc.).

FIG. 14 illustrates a flow diagram of some embodiments of a method 1400 of forming a deep trench capacitor with serrated sidewalls having a plurality of curved surfaces.

While method 1400 is illustrated and described below as a series of acts or events, it will be appreciated that the illustrated ordering of such acts or events are not to be interpreted in a limiting sense. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be carried out in one or more separate acts and/or phases.

At 1402, a conductive doped region may be formed in a substrate, in some embodiments. FIG. 8 illustrates some embodiments of a cross-sectional view 800 corresponding to act 1402.

At 1404, the substrate is selectively etched to form a trench having serrated interior surfaces with a scalloped profile defining plurality of curved depressions. In some embodiments, the serrated interior surfaces may comprise sidewalls defining a first plurality of consecutively connected curved depressions. In other embodiments, the serrated interior surfaces may comprise sidewalls defining a first plurality of discrete (i.e., non-consecutive) connected curved depressions. In some embodiments, the serrated interior surfaces may comprise a bottom surface connected between opposing sidewalls and defining a second plurality of curved depressions. FIGS. 9-10 illustrate some embodiments of cross-sectional views, 900 and 1000, corresponding to act 1404.

At 1406, a layer of dielectric material is formed within the trench. FIG. 11 illustrates some embodiments of a cross-sectional view 1100 corresponding to act 1406.

At 1408, a layer of conductive material is formed within the trench at a location separated from the substrate by the layer of dielectric material. The layer of conductive material is separated from the conductive doped region by way of the layer of dielectric material so as to form a deep trench capacitor within the trench. FIG. 12 illustrates some embodiments of a cross-sectional view 1200 corresponding to act 1408.

In some embodiments, acts 1406 and 1408 may be iteratively performed to form a plurality of alternating layers of dielectric material and conductive material. In some embodiments, the plurality of layers of dielectric material and/or conductive material may be a same dielectric material and/or conductive material, while in other embodiments the plurality of layers of dielectric material and/or conductive material may be different dielectric materials and/or conductive materials.

At 1410, a metal interconnect layer is formed in a dielectric structure over substrate. The metal interconnect layer is electrically coupled to one or more layers of the conductive material and/or the conductive doped region. FIG. 13 illustrates some embodiments of a cross-sectional view 1300 corresponding to act 1410.

Therefore, the present disclosure relates an integrated chip having a deep trench capacitor arranged within a trench comprising opposing serrated sidewalls having a plurality of curved surfaces.

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a substrate having a trench with serrated sidewalls defining a plurality of curved depressions. A layer of dielectric material conformally lines the serrated sidewalls. A layer of conductive material is separated from the substrate by the layer of dielectric material and has sidewalls comprising a plurality of curved protrusions. The layer of dielectric material is configured as capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.

In other embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a substrate having a trench comprising serrated interior surfaces, which extends from an upper surface of the substrate to an underlying position within the substrate. The trench defines an opening along the upper surface of the substrate and an underlying cavity having a larger width than the opening. A conductive doped region surrounds the trench. A layer of dielectric material conformally lines the serrated interior surfaces, and a layer of conductive material is arranged within the trench and is separated from the substrate by the layer of dielectric material.

In yet other embodiments, the present disclosure relates to a method of forming a deep trench capacitor. The method comprises selectively etching a substrate to form a trench having serrated interior surfaces defining a plurality of curved depressions. A layer of dielectric material is formed within the trench. The layer of dielectric material conformally lines the serrated interior surfaces. A layer of conductive material is formed within the trench and separated from the substrate by the layer of dielectric material. The layer of dielectric material is configured to act as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. An integrated chip, comprising: a substrate having a trench with serrated sidewalls defining a plurality of curved depressions; a layer of dielectric material conformally lining the serrated sidewalls; and a layer of conductive material separated from the substrate by the layer of dielectric material and having sidewalls comprising a plurality of curved protrusions, wherein the layer of dielectric material is configured as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.
 2. The integrated chip of claim 1, wherein a bottom surface of the trench comprises a curved profile extending between the serrated sidewalls.
 3. The integrated chip of claim 2, wherein the bottom surface comprises one or more curved depressions.
 4. The integrated chip of claim 1, wherein depths of the plurality of curved depressions into the substrate decrease as a distance from an upper surface of the substrate increases.
 5. The integrated chip of claim 1, wherein the trench comprises an opening arranged along an upper surface of the substrate and an underlying cavity in communication with the opening; and wherein the opening has a smaller width than the underlying cavity.
 6. The integrated chip of claim 5, wherein the underlying cavity has a width that increases as a distance from the upper surface of the substrate decreases.
 7. The integrated chip of claim 1, wherein the serrated sidewalls are oriented at a non-zero angle with respect to a normal line perpendicular to an upper surface of the substrate.
 8. The integrated chip of claim 1, wherein a sidewall angle of the serrated sidewalls changes as a function of a depth of the trench.
 9. The integrated chip of claim 1, wherein the plurality of curved depressions have depths that are non-uniform along a depth of the trench.
 10. The integrated chip of claim 9, wherein as the depths of the curved depressions into the substrate decrease as a distance from an upper surface of the substrate increases.
 11. The integrated chip of claim 10, wherein slopes of the serrated sidewalls increase as the depths of the curved depressions decrease.
 12. The integrated chip of claim 1, further comprising: a conductive doped region arranged within the substrate and surrounding the trench, wherein the second electrode comprises the conductive doped region.
 13. The integrated chip of claim 1, further comprising: a second layer of dielectric material conformally lining the layer of conductive material; and a second layer of conductive material conformally lining the second layer of dielectric material, wherein the second electrode comprises the second layer of conductive material.
 14. The integrated chip of claim 1, further comprising: a first conductive contact arranged within an inter-level dielectric (ILD) layer and electrically coupled to the first electrode; and a second conductive contact arranged within the inter-level dielectric (ILD) layer and electrically coupled to second electrode.
 15. An integrated chip, comprising: a substrate having a trench comprising serrated interior surfaces, which extends from an upper surface of the substrate to an underlying position within the substrate, wherein the trench defines an opening along the upper surface of the substrate and an underlying cavity having a larger width than the opening; a conductive doped region surrounding the trench; a layer of dielectric material conformally lining the serrated interior surfaces; and a layer of conductive material arranged within the trench and separated from the substrate by the layer of dielectric material.
 16. The integrated chip of claim 15, wherein a bottom surface of the trench comprises a curved surface extending between serrated sidewalls of the trench, and having one or more curved depressions.
 17. The integrated chip of claim 16, wherein the trench comprises a first serrated sidewall and a second serrated side; and wherein sidewall angles of the first serrated sidewall and the second serrated sidewall change as a function of a depth of the trench.
 18. The integrated chip of claim 15, wherein the trench curves inward along a top of the trench so that the substrate overhangs the trench along opposing sides.
 19. A method of forming a deep trench capacitor, comprising: selectively etching a substrate to form a trench having serrated interior surfaces defining a plurality of curved depressions; forming a layer of dielectric material within the trench, wherein the layer of dielectric material conformally lines the serrated interior surfaces; and forming a layer of conductive material within the trench and separated from the substrate by the layer of dielectric material, wherein the layer of dielectric material is configured to act as a capacitor dielectric between a first electrode comprising the layer of conductive material and a second electrode arranged within the substrate.
 20. The method of claim 19, wherein the serrated interior surfaces comprise sidewalls having a first plurality of curved depressions and a bottom surface connecting the sidewalls and having a second plurality of curved depressions. 